1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device of a DRAM (Dynamic Random Access Memory) type in which a self-refresh operation is constantly performed in the device.
2. Description of the Related Art
Recently, a compact mobile terminal such as a cellular phone has collaborated with the Internet and handled a large amount of data. This has stimulated a large-capacity memory. Nowadays, an SRAM (Static Random Access Memory) is employed in the cellular phones because of its low power consumption. However, the SRAM does not have a high integration density. The larger the SRAM capacity, the more expensive the cost. In contrast, the DRAM is a low-cost, high-capacity memory. The DRAM and SRAM do not have different command systems. This does not allow the SRAM to be simply interchanged with the DRAM. In this case, a major problem arises from a refresh operation of the DRAM. Data stored in memory cells of the DRAM will be lost unless the DRAM is periodically refreshed. The periodic refresh can be implemented by supplying a refresh command to the DRAM from a controller provided outside of the DRAM. However, this would apply a considerable load to the controller.
This needs a periodic refresh that is spontaneously performed within the DRAM. Such a periodic refresh is called self-refresh. If the DRAM is of asynchronous type and operates independently of a clock supplied thereto, a refresh request signal that is internally generated may collide with a request for an active operation (such as a data write or read operation) that is supplied from the outside of the DRAM.
FIG. 1 is a block diagram of a part of a core peripheral part of a conventional asynchronous DRAM. FIG. 2 is a timing chart of an operation of the configuration shown in FIG. 1.
Referring to FIG. 1, the DRAM includes a filter 10, a command control circuit 11, a refresh (REF) control circuit 12, a refresh-active (REF-ACT) comparator circuit 13, and a core control circuit 14. The REF control circuit 12 periodically supplies the REF-ACT comparator circuit 13 and the core control circuit 14 with a refresh (REF) request signal refpz. A read or write command that is supplied from the outside of the DRAM is applied to the command control circuit 11 via the filter 10. The read or write command is defined by a combination of control signals (command signals) such as a chip enable signal /CE, a write enable signal /WE, and an output enable signal /OE. The symbol xe2x80x9c/xe2x80x9d denotes an active-low signal. The filter 10 filters the command signals /CE, /WE and /OE in order to avoid malfunction of the asynchronous type DRAM due to noise. The command control circuit 11 decodes the command received via the filter 10,ad an active (ACT) request signal (that requests activation of the core) actpz to the REF-ACT comparator circuit 13 and the core control circuit 14.
The REF-ACT comparator circuit 13 selects one of the ACT request signal actpz and the REF request signal refpz that has been received earlier, and outputs a resultant REF-ACT selection signal refz to the core control circuit 14. If the refresh operation is selected, the REF-ACT selection signal refz is at a high (H) level (FIG. 2(b)). In contrast, if the ACT request signal is selected, the REF-ACT selection signal refz is at a low (L) level (FIG. 2(a)). The core control circuit 14 receives either the ACT request signal actpz or the REF request signal refpz, and operates a core (not shown for the sake of simplicity). While the core is operating, the core control circuit 14 outputs a busy signal busyz to the REF-ACT comparator circuit 13 to thus prevent the REF-ACT selection signal from switching over. If the REF request signal refpz is applied during the active operation (read or write operation), of if the ACT request signal actpz is input during the refresh operation, the later input operation is caused to wait for completion of the former input operation, and is then allowed when the former input operation is completed, that is, the busy signal busyz is switched to the L level.
FIG. 3 is circuit diagram of the REF-ACT comparator circuit 13. The circuit 13 includes inverters 15 and 16, NAND gates 17 and 18, a transfer switch 19, a latch 20 and an inverter 21. The NAND gates 17 and 18 form a flip-flop. When the ACT request signal actpz is applied to the comparator circuit 13, an output n1 of the NAND gate 17 is switched to L and an output n2 of the NAND gate 18 are both switched to H. In contrast, when the REF request signal refpz is input to the circuit 13, the output n1 is H, and the output n2 is L. When the busy signal busyz from the core control circuit 14 is L, the transfer switch 19 is ON, and n1=n3 (the output of the switch 19)=refz. In contrast when the busy signal busyz is H, the transfer switch 19 is OFF, and the output refz of the inverter 21 does not change.
FIG. 4 is a circuit diagram of a configuration of the core control circuit 14. The circuit 14 includes inverters 22, 27, 28 and 29, and NAND gates 23, 24, 25, 26, 30, 31, 32, 33 and 34. The NAND gates 23 and 24 form a flip-flop FF1, and the NAND gates 30 and 31 form a flip-flop FF2. A core control signal out, which is the output of the NAND gate 34, is output to a circuit part (not shown) involved in control of the core. When the core control signal out is H, the control of the core is started, and the busy signal busyz is switched to H. The NAND gates 26 and 32 receive the busy signal busyz. When the ACT request signal actpz and the REF request signal refpz are applied, the outputs n2 and n1 of the flip-flops FF2 and FF1 become H. When the busy signal busyz is L, the core control signal out is H. When the busy signal busyz is H, the output control signal out is L.
When the active operation is initiated (busyz=H, refz=L), the flip-flop FF2 is reset and N2=L. When the refresh operation is initiated (busyz=H, refz=H), the flip-flop FF1 is reset and N1=L. If the ACT request command actpz is applied during the refresh operation, the circuit waits for completion of the refresh operation with n2=H. When the refresh operation is completed and the busy signal busyz is switched to L, the H level of the node n2 acts as the core control signal out, and the active operation is initiated. The circuit operates in the same manner as described above when the refresh request signal refpz is applied during the active operation.
The access time in the above-mentioned control is the longest in a case where the ACT request signal is output immediately after the REF request signal refpz is applied. The longest access time needs the longest time it takes to output data. FIG. 5 is a timing chart of the above case. The access time shown in FIG. 5 is the total of the time it takes for the ACT request signal actpz to be output from an access command is input (the chip enable signal /CE switches to L, the time of the refresh operation, and the time it takes for data to be output after the ACT request signal actpz is applied.
The asynchronous type DRAM independent of the external clock needs the filter 10 to prevent the DRAM from malfunctioning due to noise that may be superimposed on the control signals such as /CE, /WE and /OE and the address signal. The signals that have passed through the filter 10 are applied to the internal circuits of the DRAM. For example, the ACT request signal actpz is generated from the signals that have passed through the filter 10. It is necessary to delay the signals by at least 1 ns in order to avoid noise equal to 1 ns. Thus, if it is attempted to eliminate noise having a relatively long width, the filter 10 is required to have a long delay. This lengthens the access time until requested data is read out from the DRAM after the corresponding command is applied thereto.
It is a general object of the present invention to provide a semiconductor memory device in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor memory device having a reduced access time.
The above objects of the present invention are achieved by a semiconductor memory device having a self-refresh operation comprising: a detection circuit generating a detection signal when detecting a change of a given input signal; and a comparator circuit comparing the detection signal with a refresh request signal internally generated and generating a control signal indicative of a circuit operation. When a change of the given signal is detected, an instruction about a circuit operation of the semiconductor memory device may be applied thereto from the outside of the device. It takes a certain time to analyze and identify the instruction because it is necessary to eliminate noise from a signal describing the instruction and decode this signal. The detection signal is generated by detecting a change of the given input signal without performing the process for interpreting an instruction described by the given input signal. The detection signal is compared with the refresh request signal. Hence, a circuit operation that is to be executed can be selected promptly.
The above objects of the present invention are also achieved by a semiconductor memory device having a self-refresh operation comprising: a detection circuit generating a detection signal when detecting a change of a given input signal; and a refresh control circuit generating a refresh request signal that requests the self-refresh operation responsive to the detection signal in a test mode. The self-refresh operation can be instructed from the outside of the device. Hence, it is possible to easily detect the access time, which corresponds to the time until data is actually read from the device after a change of the given input signal.